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d a t a sh eet product speci?cation supersedes data of 2002 apr 23 2002 dec 17 integrated circuits saa7130hl pci video broadcast decoder
2002 dec 17 2 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl contents 1 features 1.1 pci and dma bus mastering 1.2 tv video decoder and video scaling 1.3 peripheral interface 1.4 general 2 general description 2.1 introduction 2.2 overview of tv decoders with pci bridge 2.3 related documents 3 quick reference data 4 ordering information 5 block diagram 6 pinning 6.1 pins sorted by number 6.2 pins grouped by function 6.3 pin description 7 functional description 7.1 overview of internal functions 7.2 application examples 7.3 software support 7.4 pci interface 7.5 analog tv standards 7.6 video processing 7.7 analog audio pass-through and loop back cable 7.8 dtv/dvb channel decoding and ts capture 7.9 control of peripheral devices 8 boundary scan test 8.1 initialization of boundary scan circuit 8.2 device identification codes 9 limiting values 10 thermal characteristics 11 characteristics 12 package outline 13 soldering 13.1 introduction to soldering surface mount packages 13.2 reflow soldering 13.3 wave soldering 13.4 manual soldering 13.5 suitability of surface mount ic packages for wave and reflow soldering methods 14 data sheet status 15 definitions 16 disclaimers 17 purchase of philips i 2 c components
2002 dec 17 3 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 1 features 1.1 pci and dma bus mastering pci 2.2 compliant including full advanced configuration and power interface (acpi) system vendor id, etc. via eeprom hardware support for virtual addressing by mmu dma bus master write for video, vbi and ts configurable pci fifos, graceful overflow packed and planar video formats, overlay clipping. 1.2 tv video decoder and video scaling all-standards tv decoder: ntsc, pal and secam five analog video inputs: cvbs and s-video video digitizing by two 9-bit adcs at 27 mhz sampling according itu-r bt.601 with 720 pixels/line adaptive comb filter for ntsc and pal, also operating for non-standard signals automatic tv standard detection three level macrovision copy protection detection according to macrovision detect specification revision 1 control of brightness, contrast, saturation and hue versatile filter bandwidth selection horizontal and vertical downscaling or zoom adaptive anti-alias filtering capture of raw vbi samples two alternating settings for active video scaling output in yuv and rgb gamma compensation, black stretching. 1.3 tv audio i/o integrated analog audio pass-through for analog audio loop back cable to sound card. 1.4 peripheral interface i 2 c-bus master interface: 3.3 and 5 v digital video output: itu and vip formats ts input: serial or parallel general purpose i/o, e.g. for strapping and interrupt propagate reset and acpi state d3-hot. 1.5 general package: lqfp128 power supply: 3.3 v only power consumption of typical application: 1 w power-down state (d3-hot): <20 mw all interface signals 5 v tolerant reference designs available sdk for windows (95, 98, nt, 2000 and xp), video for windows (vfw) and windows driver model (wdm). 2 general description the saa7130hl is a single chip solution to digitize and decode video, and capture it through the pci-bus. special means are incorporated to maintain the synchronization of audio to video. the device offers versatile peripheral interfaces (gpio), that support various extended applications, e.g. analog audio pass-through for loop back cable to the sound card, or capture of dtv and dvb transport streams, such as vestigial side band (vsb), orthogonal frequency division multiplexing (ofdm) and quadrature amplitude modulation (qam) decoded digital television standards (see fig.1).
2002 dec 17 4 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl handbook, full pagewidth mhc169 tv tuner: ?cable ?terrestrial ?satellite digital channel decoder: ?vsb ?qam ?ofdm decoder for tv video with ts interface and dma master into pci-bus cvbs s-video audio i/o line-in line-out saa7130hl encoder: ?mpeg2 if-pll: ?dvb ?atv i 2 s-bus itu656 pci-bus ts cvbs sif dtv dvb af (mono) audio l/r i 2 c-bus eeprom audio decoder: ?btsc i 2 c-bus fig.1 application diagram for capturing live tv video in the pc, with optional extensions for enhanced dtv and dvb capture. 2.1 introduction the pci video broadcast decoder saa7130hl is a highly integrated, low cost and solid foundation for tv capture in the pc, for analog tv and digital video broadcast. the various multimedia data types are transported over the pci-bus by bus-master-write, to optimum exploit the streaming capabilities of a modern host based system. legacy requirements are also taken care of. the saa7130hl meets the requirements of pc design guides 98/99 and 2001 and is pci 2.2 and advanced configuration and power interface (acpi) compliant. the analog video is sampled by 9-bit adcs, decoded by a multi-line adaptive comb filter and scaled horizontally, vertically and by field rate. multiple video output formats (yuv and rgb) are available, including packed and planar, gamma-compensated or black-stretched. audio is routed as an analog signal via the loop back cable to the sound card. the saa7130hl provides a versatile peripheral interface to support system extensions, e.g. mpeg encoding for time shift viewing, or dsp applications for audio enhancements. the channel decoder for digital video broadcast reception (atsc or dvb) can re-use the integrated video adcs. the transport stream (ts) is collected by a tailored interface and pumped through the pci-bus to the system memory in well-defined buffer structures. various internal events, or peripheral status information, can be enabled as an interrupt on the pci-bus.
2002 dec 17 5 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 2.2 overview of tv decoders with pci bridge a tv decoder family with pci interfacing has been created to support worldwide tv broadcasting. the pin compatibility of these tv decoders offers the opportunity to support different tv broadcast standards with one pcb layout. table 1 tv decoder family with pci interfacing notes 1. x = function available. 2. dolby is a registered trademark of dolby laboratories licensing corporation. tv parameter tv decoder type (1) saa7130hl saa7133hl saa7134hl saa7135hl pci bridge version 2.2 2.2 2.2 2.2 dma channel 7 7 7 7 tv video decoding pal, ntsc and secam xxxx video scaling 2 dimension and 2 task scaler xxxx raw vbi 27 mhz sampling rate xxxx tv sound decoding fm a2 and nicam x x btsc (dbx) plus sap; eiaj x x stereo sampling (i 2 s-bus and dma) 32 khz 32 khz, 48 khz 32 khz, 48 khz radio fm radio stereo x x audio left and right pass-through xxxx stereo sampling (i 2 s-bus and dma) 32 khz, 44.1 khz, 48 khz 32 khz, 44.1 khz, 48 khz 32 khz, 44.1 khz, 48 khz video frame locked audio x x x incredible surround x x x dolby? prologic (note 2) x virtual dolby? surround x volume, bass and treble control x volume only x transport stream serial and parallel ts xxxx gpio static i/o pins 27 27 27 27 interrupt input pins 4 4 4 4 i 2 c-bus multi-master or slave xxxx video out xxxx
2002 dec 17 6 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 2.3 related documents this document describes the functionality and characteristics of the saa7130hl. other documents related to the saa7130hl are: user manual saa7130hl/34hl, describing the programmability application note saa7130hl/34hl, pointing out recommendations for system implementation demonstration and reference boards, including description, schematics, etc.: C proteus-pro: tv capture pci card for analog tv (standards: b/g, i, d/k and l/l) C europa: hybrid dvb-t and analog tv capture pci card for european broadcasting. data sheets of other devices referred to in this document, e.g: C tda8961: dtv channel decoder C td1316: atv+dvb-t tuner C tda10045: dvb channel decoder C tda9886: analog if-pll C tda9889: digital if-pll. 3 quick reference data 4 ordering information symbol parameter conditions min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v p tot total power dissipation - 1.0 - w p standby standby power dissipation d3-hot of acpi -- 0.02 w t amb ambient temperature 0 25 70 c type number package name description version saa7130hl lqfp128 plastic low pro?le quad ?at package; 128 leads; body 14 20 1.4 mm sot425-1
2002 dec 17 7 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 5 block diagram handbook, full pagewidth mhc170 analog video front-end 9-bit video adc analog video front-end ts parallel ts serial ts data ts data static i/o irq saa7130hl digital data inputs cvbs s-video inputs base- band audio inputs 9-bit video adc analog nf/audio front-end digital video comb filter decoder video scaler register unit audio output audio stereo output fifo dma pci interface pixel engine: ?matrix ?gamma ?format stereo buffer i 2 s i 2 c-bus pci-bus itu656 gpio interrupt cv4 cv3 cv2 cv1 cv0 right 2 left 2 right 1 left 1 fig.2 block diagram.
2002 dec 17 8 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 6 pinning the saa7130hl is packaged in a rectangular lqfp (low pro?le quad ?at package) with 128 pins (see fig.3). in section 6.1 all the pins are sorted by number. the pin description for the functional groups is given in tables 2 to 7: power supply pins pci interface pins analog interface pins joint test action group (jtag) test interface pins for boundary scan test i 2 c-bus multi-master interface general purpose interface (pins gpio) and the main functions. the characteristics of the pin types are detailed in table 8. 6.1 pins sorted by number symbol pin v ddd 1 gnt# 2 req# 3 ad[31] 4 ad[30] 5 ad[29] 6 ad[28] 7 ad[27] 8 ad[26] 9 ad[25] 10 ad[24] 11 c/be[3]# 12 idsel 13 ad[23] 14 ad[22] 15 ad[21] 16 ad[20] 17 ad[19] 18 v ddd 19 v ssd 20 ad[18] 21 ad[17] 22 ad[16] 23 c/be[2]# 24 frame# 25 irdy# 26 trdy# 27 devsel# 28 stop# 29 perr# 30 serr# 31 pa r 3 2 c/be[1]# 33 ad[15] 34 ad[14] 35 ad[13] 36 ad[12] 37 v ddd 38 v ssd 39 pci_clk 40 ad[11] 41 ad[10] 42 ad[09] 43 ad[08] 44 c/be[0]# 45 ad[07] 46 ad[06] 47 ad[05] 48 ad[04] 49 ad[03] 50 ad[02] 51 ad[01] 52 ad[00] 53 v ddd 54 v ssd 55 gpio23 56 gpio22 57 gpio21 58 gpio20 59 gpio19 60 gpio18 61 xtali 62 xtalo 63 v ssd 64 v ddd 65 symbol pin
2002 dec 17 9 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl v_clk 66 gpio17 67 gpio16 68 gpio15 69 gpio14 70 gpio13 71 gpio12 72 v ddd 73 v ssd 74 gpio11 75 gpio10 76 gpio9 77 gpio8 78 gpio7 79 gpio6 80 gpio5 81 gpio4 82 gpio3 83 gpio2 84 gpio1 85 gpio0 86 gpio27 87 gpio26 88 gpio25 89 scl 90 sda 91 v ddd 92 v ssd 93 left2 94 v dda 95 left1 96 v ssa 97 right1 98 v ref0 99 right2 100 v ref1 101 v ref2 102 out_right 103 out_left 104 pr op_rst 105 sif 106 symbol pin v ref3 107 v ssa 108 cv2_c 109 v dda 110 v ref4 111 drcv_y 112 v ssa 113 cv0_y 114 v dda 115 cv1_y 116 drcv_c 117 cv3_c 118 v ssa 119 cv4 120 trst 121 tck 122 tms 123 tdo 124 tdi 125 int_a 126 pci_rst# 127 v ssd 128 symbol pin
2002 dec 17 10 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 6.2 pins grouped by function table 2 power supply pins table 3 pci interface pins; note 1 symbol pin type description v ssa 97, 108, 113 and 119 ag analog ground for integrated analog signal processing v dda 95, 110 and 115 as analog supply voltage for integrated analog signal processing v ssd 20, 39, 55, 64, 74, 93 and 128 vg digital ground for digital circuit, core and i/os v ddd 1, 19, 38, 54, 65, 73 and 92 vs digital supply voltage for digital circuit, core and i/os symbol pin type description pci_clk 40 pi pci clock input: reference for all bus transactions, up to 33.33 mhz pci_rst# 127 pi pci reset input: will 3-state all pci pins (active low) ad[31] to ad[00] 4 to 11, 14 to 18, 21 to 23, 34 to 37, 41 to 44 and 46 to 53 pio and t/s multiplexed address and data input or output: bi-directional, 3-state c/be[3]# to c/be[0]# 12, 24, 33 and 45 pio and t/s command code input or output: indicates type of requested transaction and byte enable, for byte aligned transactions (active low) par 32 pio and t/s parity input or output: driven by the data source, even parity over all pins ad and c/be# frame# 25 pio and s/t/s frame input or output: driven by the current bus master (owner), to indicate the beginning and duration of a bus transaction (active low) trdy# 27 pio and s/t/s target ready input or output: driven by the addressed target, to indicate readiness for requested transaction (active low) irdy# 26 pio and s/t/s initiator ready input or output: driven by the initiator, to indicate readiness to continue transaction (active low) stop# 29 pio and s/t/s stop input or output: target is requesting the master to stop the current transaction (active low) idsel 13 pi initialization device select input: this input is used to select the saa7130hl during con?guration read and write transactions devsel# 28 pio and s/t/s device select input or output: driven by the target device, to acknowledge address decoding (active low) req# 3 po pci request output: the saa7130hl requests master access to pci-bus (active low) gnt# 2 pi pci grant input: the saa7130hl is granted to master access pci-bus (active low)
2002 dec 17 11 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl note 1. pci-bus pins are located on the long side of the package to simplify pci board layout requirements. table 4 analog interface pins; note 1 int_a 126 po and o/d interrupt a output: this pin is an open-drain interrupt output, conditions assigned by the interrupt register perr# 30 pio and s/t/s parity error input or output: the receiving device detects data parity error (active low) serr# 31 po and o/d system error output: reports address parity error (active low) symbol pin type description xtali 62 ci quartz oscillator input: 32.11 or 24.576 mhz xtalo 63 co quartz oscillator output left2 94 ai analog audio stereo left 2 input or mono input v dda 95 as analog supply voltage (3.3 v) left1 96 ai analog audio stereo left 1 input or mono input; default analog pass-through to pin out_left after reset v ssa 97 ag analog ground (for audio) right1 98 ai analog audio stereo right 1 input or mono input; default analog pass-through to pin out_right after reset v ref0 99 ar analog reference ground for audio sigma delta adc; to be connected directly to analog ground (v ssa ) right2 100 ai analog audio stereo right 2 input or mono input n.c. 101 - not connected n.c. 102 - not connected out_right 103 ao analog audio stereo right channel output; 1 v (rms) line-out, feeding the audio loop back cable via a coupling capacitor of 2.2 m f out_left 104 ao analog audio stereo left channel output; 1 v (rms) line-out, feeding the audio loop back cable via a coupling capacitor of 2.2 m f pr op_rst 105 ao analog output for test and debug purpose (active low) n.c. 106 - not connected v ref3 107 ar analog reference voltage for audio fir-dac and scart audio input buffer; to be supported with two parallel capacitors of 47 and 0.1 m f to analog ground (v ssa ) v ssa 108 ag analog ground cv2_c 109 ai composite video input (mode 2) or c input (modes 6 and 8) v dda 110 as analog power supply (3.3 v) n.c. 111 - not connected drcv_y 112 ar differential reference connection (for cv0 and cv1); to be supported with a capacitor of 47 nf to analog ground (v ssa ) v ssa 113 ag analog ground cv0_y 114 ai composite video input (mode 0) or y input (modes 6 and 8) v dda 115 as analog supply voltage (3.3 v) symbol pin type description
2002 dec 17 12 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl note 1. the saa7130hl offers an interface for analog video and audio signals. the related analog supply pins are included in this table. table 5 jtag test interface pins table 6 i 2 c-bus multi-master interface cv1_y 116 ai composite video input (mode 1) or y input (modes 7 and 9) drcv_c 117 ar differential reference connection (for cv2, cv3 and cv4); to be supported with a capacitor of 47 nf to analog ground (v ssa ) cv3_c 118 ai composite video input (mode 3) or c input (modes 7 and 9) v ssa 119 ag analog ground cv4 120 ai composite video input (mode 4) symbol pin type description trst 121 i test reset input: drive low for normal operating (active low) tck 122 i test clock input: drive low for normal operating tms 123 i test mode select input: tie high or let ?oat for normal operating tdo 124 o test serial data output: 3-state tdi 125 i test serial data input: tie high or let ?oat for normal operating symbol pin type description scl 90 io2 serial clock input (slave mode) or output (multi-master mode) sda 91 io2 serial data input and output; always available pr op_rst 105 go propagate reset and d3-hot output; to peripheral board circuitry symbol pin type description
2002 dec 17 13 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl table 7 gpio pins and functions; note 1 note 1. the saa7130hl offers a peripheral interface with general purpose input/output (gpio) pins. dedicated functions can be selected: a) digital video port (vp): output only; in 8-bit and 16-bit formats, such as vmi, dmsd (itu-r bt.601); zoom-video, with discrete sync signals; itu-r bt.656; vip (1.1 and 2.0), with sync encoded in sav and eav codes. b) transport stream (ts) capture input: from the peripheral dtv/dvb channel decoder; synchronized by start of packet (sop); in byte-parallel or bit-serial protocol. c) digitized raw dtv/dvb samples stream output: from internal adcs; to feed the peripheral dtv/dvb channel decoder. d) gpio: as default (no other function selected); static (no clock); read and write from or to individually selectable pins; latching strap information at system reset time. e) peripheral interrupt (int) input: enabled by interrupt enable register; routed to pci interrupt (int_a). symbol pin type function audio and video port outputs ts capture inputs raw dtv/dvb outputs gpio gpio27 87 gio --- r/w gpio26 88 gio --- r/w gpio25 89 gio --- r/w v_clk 66 go v_clk (also gated) - adc_clk (out) - gpio23 56 gio hsync - adc_c[0] (lsb) r/w, int gpio22 57 gio vsync ts_lock (channel decoder locked) - r/w, int gpio21 58 gio - ts_s_d (bit-serial data) - r/w gpio20 59 gio - ts_clk (<33 mhz) - r/w gpio19 60 gio - ts_sop (packet start) - r/w gpio18 61 gio vaux2 - x_clk_in r/w, int gpio17 67 gio vaux1 (e.g. vactive) - adc_y[0] (lsb) r/w gpio16 68 gio - ts_val (valid ?ag) - r/w, int gpio15 to gpio8 69 to 72 and 75 to 78 gio vp[7:0] for formats: itu-r bt.656, vmi, vip (1.1, 2.0), etc. - adc_y[8:1] r/w gpio7 to gpio0 79 to 86 gio vp extension for 16-bit formats: zv, vip-2, dmsd, etc. ts_p_d[7:0] (byte-parallel data) adc_c[8:1] r/w
2002 dec 17 14 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 6.3 pin description table 8 characteristics of pin types and remarks pin type description ag analog ground ai analog input; video, audio and sound ao analog output ar analog reference support pin as analog supply voltage (3.3 v) ci cmos input; 3.3 v level (not 5 v tolerant) co cmos output; 3.3 v level (not 5 v tolerant) gi digital input (gpio); 3.3 v level (5 v tolerant) gio digital input/output (gpio); 3.3 v level (5 v tolerant) go digital output (gpio); 3.3 v level (5 v tolerant) i jtag test input io2 digital input and output of the i 2 c-bus interface; 3.3 and 5 v compatible, auto-adapting o jtag test output o/d open-drain output (for pci-bus); multiple clients can drive low at the same time, wired-or, ?oating back to 3-state over several clock cycles pi input according to pci-bus requirements pio input and output according to pci-bus requirements po output according to pci-bus requirements s/t/s sustained 3-state (for pci-bus); previous owner drives high for one clock cycle before leaving to 3-state t/s 3-state i/o (for pci-bus); bi-directional vg ground for digital supply vs supply voltage (3.3 v) with overscore or # this pin or signal is active low, i.e. the function is true if the logic level is low
2002 dec 17 15 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl handbook, full pagewidth mhc168 saa7130hl 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 101 102 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 40 39 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 127 128 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 v ddd gnt# req# ad[31] ad[30] ad[29] ad[28] ad[27] ad[26] ad[25] ad[24] c/be[3]# idsel ad[23] ad[22] ad[21] ad[20] ad[19] v ddd v ssd ad[18] ad[17] ad[16] c/be[2]# frame# irdy# trdy# devsel# stop# perr# serr# par c/be[1]# ad[15] ad[14] ad[13] ad[12] v ddd n.c. n.c. right2 v ref0 right1 v ssa left1 v dda left2 v ssd v ddd sda scl gpio25 gpio26 gpio27 gpio0 gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 gpio7 gpio8 gpio9 gpio10 gpio11 v ssd v ddd gpio12 gpio13 gpio14 gpio15 gpio16 gpio17 v_clk v ddd cv4 v ssa cv3_c drcv_c cv1_y v dda cv0_y v ssa drcv_y n.c. v ssd int_a tdi tdo tms tck trst v dda cv2_c v ssa v ref3 n.c. prop_rst out_left out_right ad[06] ad[05] ad[04] ad[03] ad[02] ad[01] ad[00] v ddd v ssd gpio23 v ssd pci_clk ad[11] ad[10] ad[09] ad[08] c/be[0]# ad[07] gpio22 gpio21 gpio20 gpio19 gpio18 xtali xtalo v ssd pci_rst# fig.3 pin configuration.
2002 dec 17 16 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 7 functional description 7.1 overview of internal functions the saa7130hl is able to capture tv signals over the pci-bus in personal computers by a single chip (see fig.4). mhc171 handbook, full pagewidth clamp and gain control input selection decoder (ntsc, pal, secam) adaptive comb filter video scaler raw vbi program set program set 3-d 9-bit adc 9-bit adc matrix format gamma video port (digital) digital video output 5 analog video inputs transport stream input reset gpio stereo output stereo input 1 stereo input 2 propagate reset oscillator crystal test saa7130hl boundary scan test acpi power management llc i 2 c-bus interface i 2 c-bus i 2 s-bus input dtv-ts p/s analog audio i/o pass-through (default) video fifos pci-bus interface pci-bus dma control ts fifos dma control fig.4 functional block diagram.
2002 dec 17 17 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl the saa7130hl incorporates two 9-bit video adcs and the entire decoding circuitry of any analog tv signal: ntsc, pal and secam, including non-standard signals, such as playback from a vcr. the adaptive multi-line comb filter provides superb picture quality, component separation, sharpness and high bandwidth. the video stream can be cropped and scaled to the needs of the application. scaling down as well as zooming up is supported in the horizontal and vertical direction, and an adaptive filter algorithm prevents aliasing artifacts. with the acquisition unit of the scaler two different tasks can be defined, e.g. to capture video to the cpu for compression, and write video to the screen from the same video source but with different resolution, colour format and frame rate. the saa7130hl incorporates analog audio pass-through and support for the analog audio loop back cable to the sound card function. the decoded video streams are fed to the pci-bus, and are also applied to a peripheral streaming interface, in itu, vip or vmi format. a possible application extension is on-board hardware mpeg compression, or other feature processing. the compressed data is fed back through the peripheral interface, in parallel or serial format, to be captured by the system memory through the pci-bus. the transport stream (ts) from a dtv/dvb channel decoder can be captured through the peripheral interface in the same way. video and transport streams are collected in a configurable fifo with a total capacity of 1 kbyte. the dma controller monitors the fifo filling degree and master-writes the audio and video stream to the associated dma channel. the virtual memory address space (from os) is translated into physical (bus) addresses by the on-chip hardware memory management unit (mmu). the application of the saa7130hl is supported by reference designs and a set of drivers for the windows operating system (video for windows and windows driver model compliant). 7.2 application examples the saa7130hl enables pc tv capture applications both on the pc mother board and on pci add-on tv capture cards. figures 5 and 6 illustrate some examples of add-on card applications. figure 5 shows the basic application to capture video from analog tv sources. the proposed tuner types incorporate the rf tuning function and the if downconversion. usually the if downconversion stage also includes a single channel and analog sound fm demodulator. the philips tuner fi1216mk2 is dedicated to the 50 hz system b/g standard as used in europe. the fi1236mk2 is the comparable type for the 60 hz system m standard for the usa. both types are suited for terrestrial broadcast and for cable reception. the tuner provides composite video and baseband audio as mono or multiplexed (mpx) in case of btsc. these analog video and sound signals are fed to the appropriate input pins of the saa7130hl. further analog video input signals, cvbs and/or y-c, can be connected via the board back-panel, or the separate front connectors, e.g. from a camcorder. accompanying stereo audio signals can also be fed to the saa7130hl. video is digitized and decoded to yuv. the digital streams are pumped via dma into the pci memory space. the saa7130hl incorporates means for legacy analog audio signal routing. the analog audio input signal is fed via an analog audio loop back cable into the line-in of a legacy sound card. an external audio signal, that would have otherwise connected directly to the sound card, is now routed through the saa7130hl. this analog pass-through is enabled as default by a system reset, i.e. without any driver involvement and before system set-up. during the power-up procedure, the saa7130hl will investigate the on-board eeprom to load the board specific system vendor id and board version id into the related places of the pci configuration space. the board vendor can store other board specific data in the eeprom that is accessible via the i 2 c-bus.
2002 dec 17 18 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl handbook, full pagewidth mhc172 cvbs pci-bus: digital video, raw vbi, ts cvbs s-video audio line-in isa agp fsb af sound (mono) saa7130hl i 2 c-bus eeprom i 2 c-bus tv tuner and if-pll tv cable or terrestrial analog audio loop back cable system vendor id sound card north bridge south bridge tv capture pci card system memory vga and local memory cpu and cache memory dma master into pci decoder for tv video fig.5 tv mono capture card.
2002 dec 17 19 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl handbook, full pagewidth mhc173 cvbs if if cvbs s-video audio line-in isa agp fsb af ts saa7130hl i 2 c-bus eeprom i 2 c-bus analog if-pll atv cable or terrestrial and dvb terrestrial tv tuner digital if-pll dvb-t channel decoder system vendor id sound card north bridge south bridge hybrid tv capture pci card system memory vga and local memory cpu and cache memory dma master into pci decoder for tv video pci-bus: digital video, raw vbi, ts analog audio loop back cable fig.6 hybrid tv capture board for digital tv (dvb-t) and analog tv reception. figure 6 shows an application extension with a hybrid tv tuner front-end and digital terrestrial channel decoding for dtv-t. the single-conversion tuner td1316 provides two dedicated if signals for the analog if-pll (tda9886) and the digital if-pll (tda9889). the cvbs (video) and aud (audio, mono) output signals of the analog if-pll can be routed to one of the video inputs and the audio (left or right) input of the saa7130hl for analog video decoding and direct audio streaming to the sound card. on the other hand, the 2nd if signal of the digital if-pll is fed directly to the interface of the channel decoder (tda10045), which decodes the signal into a digital dvb-t transport stream (ts). the saa7130hl captures this ts via the dedicated peripheral interface into the configurable internal fifo for dma into the pci memory space. the packet structure as decoded by the tda10045 is maintained in a well-defined buffer structure in the system memory, and therefore can easily be sorted (de-multiplexed) by the cpu for proper mpeg decoding. the broadcast driver architecture (bda) for windows operating systems supports this type of hybrid tv capture application, sharing one capture board for analog and digital tv reception.
2002 dec 17 20 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 7.3 software support 7.3.1 d evice driver a complex and powerful software packet is provided for the saa7130hl. this packet includes plug-and-play driver and capture driver installations for all commonly used 32-bit windows platforms. all platform related drivers support the following: video preview and capture interfaces audio control and audio capture interfaces custom application interface, that enables the development of specialized applications in cases where the published windows application program interface (api) such as wdm or vfw is not sufficient. table 9 microsoft operation system (mos) support mos driver support windows 95 device access is contained within a vxd. the video for windows (vfw) capture driver interface is a 16-bit user-mode interface. windows nt4 device access is contained in a kernel-mode driver. the vfw capture driver interface is a 32-bit user-mode interface. windows 98 device access is contained with a kernel-mode windows driver model (wdm) driver. the capture driver interface is also kernel-mode wdm. windows 2000 the driver is binary-compatible with the windows 98 driver. windows me the driver is binary-compatible with the windows 98 driver. windows xp the driver is binary-compatible with the windows 98 driver. 7.3.2 s upporting wdm the wdm driver for windows 98 and windows 2000 (see fig.7) is a kernel-mode driver that implements a kernel streaming (ks) filter with output pins for audio, video preview, video capture and vbi, together with a crossbar for input source selection and optional connections for other on-board devices as child drivers. the wdm driver is implemented as a stream class mini-driver. it also exposes the external interfaces to support the user-mode 34api dll. custom applications and debug tools will continue to work without the need to load different drivers. handbook, full pagewidth mhc174 xbar tv tuner saa7130hl capture driver external video inputs audio inputs transport stream in video preview video capture vbi fig.7 wdm capture driver filters.
2002 dec 17 21 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 7.3.3 s upporting vfw the traditional video for windows (vfw) interface is supported for windows 9x and for windows nt4.0 (see fig.8). in both cases a 32-bit capture driver based on the saa713x user-mode api (34api.dll) controls the video functionality and the user-mode audio driver implementation. the capture driver supports direct draw surfaces for live video and is able to capture video in packed data formats and in planar formats. tv applications such as intel intercast and philips teletext are supported by a private vbi extension. in the event that vfw has to be implemented as a 16-bit interface under windows 9x, a thunk layer is included for connecting the 16-bit interface to the 32-bit capture driver. old 16-bit applications using vfw are still supported in this way. 7.3.4 s oftware development kit for customer related applications in addition to the capture driver, an application programmers interface (api) dynamic linked library (dll) provides the whole range of functionality to control the device (see fig.9). this class library is built in c++ and provides methods to: capture video into a fixed buffer (including clipping) capture video to a stream of buffers over vbi capture transport streams (mpeg data) from a channel decoder chip (ofdm, vsb, qam) for supporting digital tv applications, or from an on-board mpeg encoder chip that is fed by the video output port of the saa7130hl capture raw vbi sample stream to a stream of buffers over the pci-bus access to the i 2 c-bus master for controlling other peripheral circuits. the 34api transfers the device driver functionality through a proxy interface to the user-mode. the proxy interface adapts to the different kernel-mode implementations, so that the common 34api can be used on all windows operating systems in the same way. the sdk for the saa7130hl contains the detailed description of all software components such as api documentation for streaming, tuner control, dialogues and direct draw control. the provided sample code will introduce the user into working with this interface. all necessary header and library files are provided. vidcap (win 9x) 34vcap16.dll 34vcap32.exe vidcap32 (win nt4.0) 34w95.vxd 34api.dll 34vcap32.dll vbi extension for intercast, cc, txt mhb994 fig.8 vfw driver structure. 34wdm.sys 34w95.vxd 34nt4.sys 34api.dll 34vcap.dll mhb995 fig.9 user program interface.
2002 dec 17 22 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 7.4 pci interface 7.4.1 pci configuration registers the pci interface of the saa7130hl complies with the pci specification 2.2 and supports power management and advanced configuration and power interface (acpi) as required by the pc design guide 2001 . the pci specification defines a structure of the pci configuration space that is investigated during the boot-up of the system. the configuration registers (see table 10) hold information essential for plug-and-play, to allow system enumeration and basic device set-up without depending on the device driver, and support association of the proper software driver. some of the configuration information is hard-wired in the device; some information is loaded during the system start-up. the device vendor id is hard coded to 11 31h, which is the code for philips as registered with pci-sig. the device id is hard coded to 71 30h. during power-up, initiated by pci reset, the saa7130hl fetches additional system information via the i 2 c-bus from the on-board eeprom, to load actual board type specific codes for the system vendor id, sub-system id (board version) and acpi related parameters into the configuration registers. 7.4.2 acpi and power states the pci specification 2.2 requires support of advanced configuration and power interface specification 1.0 (acpi); more details are defined in the pci power management specification 1.0 . the power management capabilities and power states are reported in the extended configuration space. the main purpose of acpi and pci power management is to tailor the power consumption of the device to the actual needs. the saa7130hl supports all four acpi device power states (see table 11). the pin prop_rst of the peripheral interface is switched active low during the pci reset procedure, and for the duration of the d3-hot state. peripheral devices on board of the add-on card should use the level of this signal prop_rst to switch themselves in any power-save mode (e.g. disable device) and reset to default settings on the rising edge of signal prop_rst. table 10 pci con?guration registers note 1. x = dont care. function register address (hex) value (hex) remark device vendor id 00 and 01 11 31 for philips device id 02 and 03 71 30 for saa7130hl revision id 08 00 or higher class code 09 to 0b 04 80 00 multimedia memory address space required 10 to 13 xxxxxxxx xxxxxxxx xxxxxx00 00000000 (b) 1 kbyte; note 1 system (board) vendor id 2c and 2d loaded from eeprom sub-system (board version) id 2e and 2f loaded from eeprom
2002 dec 17 23 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl table 11 power management table power state description d0 normal operation: all functions accessible and programmable. the default setting after reset and before driver interaction (d0 un-initialized) switches most of the circuitry of the saa7130hl into the power-down mode, effectively such as d3-hot. d1 first step of reduced power consumption: no functional operation; program registers are not accessible, but content is maintained. most of the circuitry of the saa7130hl is disabled with exception of the crystal and real-time clock oscillators, so that a quick recovery from d1 to d0 is possible. d2 second step of reduced power consumption: no functional operation; program registers are not accessible, but content is maintained. all functional circuitry of the saa7130hl is disabled, including the crystal and clock oscillators. d3-hot lowest power consumption: no functional operation. the content of the programming registers gets lost and is set to default values when returning to d0. 7.4.3 dma and configurable fifo the saa7130hl supports seven dma channels to master-write captured active video, raw vbi and dtv/dvb transport streams (ts) into the pci memory. each dma channel contains inherently the definition of two buffers, e.g. for odd and even fields in case of interlaced video. the dma channels share in time and space one common fifo pool of 256 dwords (1024 bytes) total. it is freely configurable how much fifo capacity can be associated with which dma channel. furthermore, a preferred minimum burst length can be programmed, i.e. the amount of data to be collected before the request for the pci-bus is issued. this means that latency behaviour per dma channel can be tailored and optimized for a given application. in the event that a fifo of a certain channel overflows due to latency conflict on the bus, graceful overflow recovery is applied. the mount of data that gets lost because it could not be transmitted, is monitored (counted) and the pci-bus address pointer is incremented accordingly. thus new data will be written to the correct memory place, after the latency conflict is resolved. 7.4.4 v irtual and physical addressing most operating systems allocate memory to requesting applications for dma as continuous ranges in virtual address space. the data flow over the pci-bus points to physical addresses, usually not continuous and split in pages of 4 kbytes (intel architecture, most unix systems, power pc). the association between the virtual (logic) address space and the fragmented physical address space is defined in page tables (system files); see fig.10. the saa7130hl incorporates hardware support (mmu) to translate virtual to physical addresses on the fly, by investigating the related page table information. this hardware support reduces the demand for real-time software interaction and interrupt requests, and therefore saves system resources. 7.4.5 s tatus and interrupts on pci- bus the saa7130hl provides a set of status information about internal signal processing, video standard detection, peripheral inputs and outputs (pins gpio) and behaviour on the pci-bus. this status information can be conditionally enabled to raise an interrupt on the pci-bus, e.g. completion of a certain dma channel or buffer, or change in a detected tv standard, or the state of peripheral devices. the cause of an issued interrupt is reported in a dedicated register, even if the original condition has changed before the system was able to investigate the interrupt.
2002 dec 17 24 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl handbook, full pagewidth mhb996 physical memory = allocated memory space = page table 00000h 00007h 0000fh 00017h 0001fh 000h 007h 015h page table 0000a000h 00001000h 00011000h 00008000h 00009000h 0000d000h 00014000h 00016000h 0001e000h pci transfer and control virtual to physical address translation dma address generation fifo pool dma definitions (virtual address space) real-time streams physical address space on pci fig.10 mmu implementation (shown bit width indication is valid for 4 kbytes mode).
2002 dec 17 25 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 7.5 analog tv standards analog tv signals are described in three categories of standards: basic tv systems: defining frame rate, number of lines per field, levels of synchronization signals, blanking, black and white, signal bandwidth and the rf modulation scheme colour transmission: defining colour coding and modulation method sound and stereo: defining coding for transmission. tv signals that are broadcasted usually conform fairly accurately to the standards. transmission over the air or through a cable can distort the signal with noise, echoes, crosstalk or other disturbances. video signals from local consumer equipment, e.g. vcr, camcorder, camera, game console, or even dvd player, often do not follow the standard specification very accurately. playback from video tape cannot be expected to maintain correct timing, especially not during feature mode (fast forward, etc.). tables 12, 13 and 14 list some characteristics of the various tv standards. the saa7130hl decodes all colour tv standards and non-standard signals as generated by video tape recorders e.g. automatic video standard detection can be applied, with preference options for certain standards, or the decoder can be forced to a dedicated standard. table 12 overview of basic tv standards main parameters standard unit m n b g, h i d/k l rf channel width 6 6 7 7 8 7 8 mhz video bandwidth 4.2 4.2 5 5 5.5 6 6 mhz 1st sound carrier 4.5, fm 4.5, fm 5.5, fm 5.5, fm 6.0, fm 6.5, fm 6.5, am mhz field rate 59.94006 50 50 50 50 50 50 hz lines per frame 525 625 625 625 625 625 625 - line frequency 15.734 15.625 15.625 15.625 15.625 15.625 15.625 khz itu clocks per line 1716 1728 1728 1728 1728 1728 1728 - sync, set-up level - 40, 7.5 - 40, 7.5 - 43, 0 - 43, 0 - 43, 0 - 43, 0 - 43, 0 ire gamma correction 2.2 2.2 2.8 2.8 2.8 2.8 2.8 - associated colour tv standards ntsc, pal pal pal pal pal secam, pa l secam - associated stereo tv sound systems btsc, eiaj, a2 btsc dual fm, a2 nicam nicam nicam, a2 nicam - country examples usa, japan, brazil argentina part of europe, australia spain, malaysia, singapore uk, northern europe china, eastern europe france, eastern europe -
2002 dec 17 26 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl table 13 tv system colour standards table 14 tv stereo sound standards main parameters ntsc m pal m pal n pal bghid secam ldghk pal 4.4 (60 hz) unit field rate 59.94 59.94 50 50 50 ? 60 hz lines per frame 525 525 625 625 625 525 chrominance subcarrier 3.580 3.576 3.582 4.434 4.406 4.250 4.434 mhz f sc to h ratio 227.5 227.25 229.25 283.75 282 272 n.a. f sc offset (pal) -- 50 50 -- n.a. hz alternating phase no yes yes yes -- yes country examples usa, japan, asia-paci?c brazil middle and south america europe, common- wealth, china france, eastern europe, africa, middle east vcr transcoding ntsc-tape to pal main parameters analog systems digital coding unit mono btsc eiaj a2 (dual fm) nicam stereo coding scheme - internal carrier (mpx) 2-carrier systems (2cs) am fm 2nd fm carrier dqpsk on fm 2nd language - mono sap on internal fm as alternative to stereo as alternative to stereo mono on 1st carrier sound if 1st 2nd 1st 2nd m, n 4.5 fm 4.5 4.5 4.5 4.724 not used not used mhz b, g, h 5.5 fm not used not used 5.5 5.742 5.5 5.850 mhz i 6.0 fm not used not used not used not used 6.0 6.552 mhz dk (1) 6.5 fm not used not used 6.5 6.742 6.5 5.850 mhz dk (2) 6.5 fm --- 6.258 -- mhz dk (3) 6.5 fm --- 5.742 -- mhz l 6.5 am not used not used not used not used 6.5 5.850 mhz de-emphasis 75 75, dbx 50 50 or 75 50 or j17 m s audio bandwidth 15 15 15 15 15 khz country examples world- wide usa, south america japan part of europe, korea part of europe, china
2002 dec 17 27 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 7.6 video processing 7.6.1 a nalog video inputs the saa7130hl provides five analog video input pins: composite video signals (cvbs), from tuner or external source s-video signals (pairs of y-c), e.g. from camcorder dtv/dvb low-if signal, from an appropriate dtv or combi-tuner. analog anti-alias filters are integrated on chip and therefore, no external filters are required. the device also contains automatic clamp and gain control for the video input signals, to ensure optimum utilization of the adc conversion range. the nominal video signal amplitude is 1 v (p-p) and the gain control can adapt deviating signal levels in the range of +3 db to - 6 db. the video inputs are digitized by two adcs of 9-bit resolution, with a sampling rate of nominal 27 mhz (the line-locked clock) for analog video signals. 7.6.2 v ideo synchronization and line - locked clock the saa7130hl recovers horizontal and vertical synchronization signals from the selected video input signal, even under extremely adverse conditions and signal distortions. such distortions are noise, static or dynamic echoes from broadcast over air, crosstalk from neighbouring channels or power lines (hum), cable reflections, time base errors from video tape play-back and non-standard signal levels from consumer type video equipment (e.g. cameras, dvd). the heart of this tv synchronization system is the generation of the line-locked clock (llc) of nominal 27 mhz, as defined by itu-r bt.601. the llc ensures orthogonal sampling, and always provides a regular pattern of synchronization signals, that is a fixed and well defined number of clock pulses per line. this is important for further video processing devices connected to the peripheral video port (pins gpio). it is very effective to run under the llc of 27 mhz, especially for on-board hardware mpeg encoding devices, since mpeg is defined on this clock and sampling frequency. 7.6.3 v ideo decoding and automatic standard detection the saa7130hl incorporates colour decoding for any analog tv signal. all colour tv standards and flavours of ntsc, pal, secam and non-standard signals (vcr) are automatically recognized and decoded into luminance and chrominance components, i.e. y-c b -c r , also known as yuv. the video decoder of the saa7130hl incorporates an automatic standard detection, that does not only distinguish between 50 and 60 hz systems, but also determines the colour standard of the video input signal. various preferences (look first) for automatic standard detection can be chosen, or a selected standard can be forced directly. 7.6.4 a daptive comb filter the saa7130hl applies adaptive comb filter techniques to improve the separation of luminance and chrominance components in comparison to the separation by a chroma notch filter, as used in traditional tv colour decoder technology. the comb filter compares the signals of neighbouring lines, taking into account the phase shift of the chroma subcarrier from line to line. for ntsc the signal from three adjacent lines are investigated, and in the event of pal the comb filter taps are spread over four lines. comb filtering achieves higher luminance bandwidth, resulting in sharper picture and detailed resolution. comb filtering further minimizes colour crosstalk artifacts, which would otherwise produce erroneous colours on detailed luminance structures. the comb filter as implemented in the saa7130hl is adaptive in two ways: adaptive to transitions in the picture content adaptive to non-standard signals (e.g. vcr). the integrated digital delay lines are always exactly correct, due to the applied unique line-locked sampling scheme (llc). therefore the comb filter does not need to be switched off for non-standard signals and remains operating continuously. 7.6.5 m acrovision detection the saa7130hl detects if the decoded video signal is copy protected by the macrovision system. the detection logic distinguishes the three levels of the copy protection as defined in rev. 7.01, and are reported as status information. the decoded video stream is not effected directly, but application software and operation system (os) has to ensure, that this video stream maintains tagged as copy protected, and such video signal would leave the system only with the reinforced copy protection. the multi-level macrovision detection on the video capture side supports proper tv re-encoding on the output point, e.g. by philips tv encoders saa712x or saa7102.
2002 dec 17 28 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 7.6.6 v ideo scaling the saa7130hl incorporates a filter and processing unit to downscale or upscale the video picture in the horizontal and vertical dimension, and in frame rate (see figs 11 and 12). the phase accuracy of the re-sampling process is 1 64 of the original sample distance. this is equivalent to a clock jitter of less than 1 ns. the filter depth of the anti-alias filter adapts to the scaling ratio, from 10 taps horizontally for scaling ratios close to 1 : 1, to up to 74 taps for an icon sized video picture. most video capture applications will typically require for downscaling. but some zooming is required for conversion of itu sampling to square pixel (sqp), or to convert the 240 lines of an ntsc field to 288 lines to comply with ccitt video phone formats. the scaling acquisition definition also includes cropping, frame rate reduction, and defines the amount of pixels and lines to be transported through dma over the pci-bus. two programming pages are available to enable re-programming of the scaler in the shadow of the running processing, without holding or disturbing the flow of the video stream. alternatively, the two programming pages can be applied to support two video destinations or applications with different scaler settings, e.g. firstly to capture video to cpu for compression (storage, video phone), and secondly to pre-view the picture on the monitor screen. a separate scaling region is dedicated to capture raw vbi samples, with a specific sampling rate, and be written into its own dma channel. handbook, full pagewidth mhb997 active video area video region - cropped - scaled scaling vbi dma video dma (a) e.g. interlaced 1st buffer (upper field) 2nd buffer (lower field) vbi first sample 1st buffer (a) 2nd buffer (a) vbi region, raw samples vbi last sample video first pixel video last pixel vbi last line vbi first line sample rate 1st field (odd, fid = 0) active video area video region - cropped - scaled scaling vbi region, raw samples video last line video first line sample rate 2nd field (even, fid = 1) fig.11 scaler processing with dma interfacing. the capture acquisition for scaling and dma has separate programming parameters for vbi and video region and associated dma channels.
2002 dec 17 29 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl handbook, full pagewidth mhb998 vbi dma 1st buffer (a) 2nd buffer (a) 3rd buffer (b) 4th buffer (b) video dma (a) e.g. interlaced 1st buffer (upper field) 2nd buffer (lower field) video dma (b) e.g. single fid 1st buffer 2nd buffer (next frame) active video area video region (a) - cropped scaling vbi region, raw samples sample rate 1st field (odd, fid = 0) active video area video region (a) - cropped scaling vbi region, raw samples sample rate 2nd field (even, fid = 1) active video area video region (b) - skipped for field rate reduction vbi region, raw samples sample rate 3rd field (odd, fid = 0) active video area task "b" task "a" alternating processing task a/b video region - scaled down cif scaling vbi region, raw samples sample rate 4th field (even, fid = 1) fig.12 scaler task processing with dma interfacing. two video capture tasks can be processed in an alternating manner, without need to reprogram any scaling parameters or dma definition.
2002 dec 17 30 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 7.6.7 vbi data the vertical blanking interval (vbi) is often utilized to transport data over analog video broadcast. such data can closely relate to the actual video stream, or just be general data (e.g. news). some examples for vbi data types are: closed caption (cc) for the hearing impaired (cc, on line 21 of first field) intercast data [in us coded in north-american broadcast text system (nabts) format, in europe in world standard teletext (wst)], to transmit internet related services, optionally associated with actual video program content teletext, transporting news services and broadcast related information, electronic program guide (epg), widely used in europe (coded in wst format) epg, broadcaster specific program and schedule information, sometimes with proprietary coding scheme (pay service), usually carried on nabts, wst, video programming service (vps), or proprietary data coding format video time codes (vtc) as inserted in camcorders e.g. use for video editing copy guard management system (cgms) codes, to indicate copy protected video material, sometimes combined with format information [wide screen signalling (wss)]. this information is coded in the unused lines of the vertical blanking interval, between the vertical sync pulse and the active visible video picture. so-called full-field data transmission is also possible, utilizing all video lines for data coding. the saa7130hl supports capture of vbi data by the definition of a vbi region to be captured as raw vbi samples, that will be sliced and decoded by software on the host cpu. the raw sample stream is taken directly from the adc and is not processed or filtered by the video decoder. the sampling rate of raw vbi can be adjusted to the needs of the data slicing software. 7.6.8 s ignal levels and colour space analog tv video signals are decoded into its components luminance and colour difference signals (yuv) or in its digital form y-c b -c r . itu-r bt.601 defines 720 pixels along the line (corresponding to a sampling rate of 27 mhz divided by two), and a certain relationship from level to number range (see fig.13). the video components do not use the entire number range, but leave some margin for overshoots and intermediate values during processing. for the raw vbi samples there is no official specification how to code, but it is common practice to reserve the lower quarter of the number range for the sync, and to leave some room for overmodulation beyond the nominal white amplitude (see fig.14). the automatic clamp and gain control at the video input, together with the automatic chroma gain control of the saa7130hl, ensures that the video components stream at the output comply to the standard levels. beyond that additional brightness, contrast, saturation and hue control can be applied to satisfy special needs of a given application. the raw vbi samples can be adjusted independent of the active video. the saa7130hl incorporates the yuv-to-rgb matrix (optional), the rgb-to-yuv matrix and a three channel look-up table in between (see fig.15). under nominal settings, the rgb space will use the same number range as defined by the itu and shown in fig.13a for luminance, between 16 and 235. as graphic related applications are based on full-scale rgb, i.e. 0 to 255, the range can be stretched by applying appropriate brightness, contrast and saturation values. the look-up table supports gamma correction (freely definable), and allows other non-linear signal transformation such as black stretching. the analog tv signal applies a quite strong gamma pre-compensation (2.2 for ntsc and 2.8 for pal). as computer monitors exhibit a gamma (around 2.5), the difference between gamma pre-compensation and actual screen gamma has to be corrected, to achieve best contrast and colour impression. the saa7130hl offers a multitude of formats to write video streams over the pci-bus: yuv and rgb colour space, 15-bit, 16-bit, 24-bit and 32-bit representation, packed and planar formats. for legacy requirements (vfw) a clipping procedure is implemented, that allows the definition of 8 overlay rectangles. this process can alternatively be used to associate alpha values to the video pixels.
2002 dec 17 31 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl luminance 100% + 255 + 235 + 128 + 16 0 white black u-component + 255 + 240 + 212 + 212 + 128 + 16 + 44 0 blue 100% blue 75% yellow 75% yellow 100% colourless v-component + 255 + 240 + 128 + 16 + 44 0 red 100% red 75% cyan 75% cyan 100% colourless mgc634 fig.13 nominal digital levels for yuv (y-c b -c r ) in accordance with itu-r bt.601. a. y output range. b. u output range (c b ). c. v output range (c r ). luminance + 255 + 209 + 71 + 60 1 white sync bottom black shoulder black sync luminance + 255 + 199 + 60 1 white sync bottom black shoulder = black sync mgd700 fig.14 nominal digital levels for cvbs and raw vbi samples. a. sources containing 7.5 ire black level offset (e.g. ntsc m). b. sources not containing black level offset.
2002 dec 17 32 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl handbook, full pagewidth mhb999 r g b y u v yuv to rgb matrix r g b y u v rgb to yuv matrix three channel non-linear transformation fig.15 colour space conversion and look-up table. 7.6.9 v ideo port , itu and vip codes the decoded and/or scaled video stream can be captured via pci-dma to the system memory, and/or can be made available locally through the video side port (vp), using some of the gpio pins. two types of applications are intended: streaming real-time video to a video side port at the vga card, e.g. via ribbon cable over the top feeding video stream to a local mpeg compression device on the same pci board, e.g. for time shift viewing applications. the video port of the saa7130hl supports the following 8 and 16-bit wide yuv video signalling standards (see table 7): vmi: 8-bit wide data stream, clocked by llc = 27 mhz, with discrete sync signals hsync, vsync and vactive itu-r bt.656, parallel: 8-bit wide data stream, clocked by llc = 27 mhz, synchronization coded in sav and eav codes vip 1.1 and 2.0: 8-bit or 16-bit wide data stream, clocked by llc = 27 mhz, synchronization coded in sav and eav codes (with vip extensions) zoom video (zv): 16-bit wide pixel stream, clocked by llc/2 = 13.5 mhz, with discrete sync signals hsync and vsync itu-r bt.601 direct (dmsd): 16-bit wide pixel stream, clocked by llc = 27 mhz, with discrete sync signals hsync, vsync/fid and cref raw dtv/dvb sample stream: 9-bit wide data, clocked with a copy of signal x_clk_in. the vip standard can transport scaled video and discontinuous data stream by allowing the insertion of 00 as marker for empty clock cycles. for the other video port standards, a data valid flag or gated clock can be applied. 7.7 analog audio pass-through and loop back cable most operating systems are prepared to deal with audio input at only one single entry point, namely at the sound card function. therefore the sound associated with video has to get routed through the sound card. the saa7130hl supports analog audio pass-through and the loop back cable on-chip. no external components are required. the audio signal, that was otherwise connected to the sound card line-in, e.g. analog sound from a cd-rom drive, has to be connected to one of the inputs of the saa7130hl. by default, after a system reset and without involvement of any driver, this audio signal is passed through to the analog audio output pins, that will feed the loop back cable to the sound card line-in connector. the av capture driver has to open the default pass-through and switch in the tv sound signal by will.
2002 dec 17 33 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 7.8 dtv/dvb channel decoding and ts capture the saa7130hl is optimum equipped to support the application extension to capture digital tv signals, e.g. for vsb (atsc) or dvb (t/c/s). a hybrid tv tuner for analog and digital tv broadcast reception usually provides a dtv signal on low if, i.e. downconverted into a frequency range from 0 to 10 mhz. such signals can be fed to one of the 5 video inputs of the saa7130hl for digitizing. the digital raw dtv is output at the video port, and is sent to the peripheral channel decoder, e.g. tda8961 for vsb-8 decoding. the channel decoder provides the sampling clock via the external clock input pin x_clk_in (up to 36 mhz input clock frequency), and adjusts the signal gain in the tuner or in the video input path in front of the adc. alternatively, the low if dtv/dvb signal could be fed directly to the channel decoder, depending on the capability for digitizing the selected device. the peripheral channel decoder circuitry decodes the digital transmission into bits and bytes, apply error correction etc., and outputs a packed transport stream (ts) accompanied by a clock and handshake signals. the saa7130hl captures the ts in parallel or serial protocol, synchronized by start of packet (sop), and pumps it via the dedicated dma into the pci memory space. the dma definition supports automatic toggling between two buffers. 7.9 control of peripheral devices 7.9.1 i 2 c- bus master the saa7130hl incorporates an i 2 c-bus master to set-up and control peripheral devices such as tuner, dtv/dvb channel decoder, audio dsp co-processors, etc. the i 2 c-bus interface itself is controlled from the pci-bus on a command level, reading and writing byte by byte. the actual i 2 c-bus status is reported (status register) and, as an option, can raise error interrupts on the pci-bus. at pci reset time, the i 2 c-bus master receives board specific information from the on-board eeprom to update the pci configuration registers. the i 2 c-bus interface is multi-master capable and can assume slave operation too. this allows application of the device in the stand-alone mode, i.e. with the pci-bus not connected. under the slave mode, all internal programming registers can be reached via the i 2 c-bus with exception of the pci configuration space. 7.9.2 p ropagate reset the pci system reset and acpi power management state d3 is propagated to peripheral devices by the dedicated pin prop_rst. this signal is switched to active low by reset and d3, and is only switched high under control of the device driver by will. the intention is that peripheral devices will use signal prop_rst as chip-enable (ce). the peripheral devices should enter a low power consumption state if pin prop_rst = low, and reset into default setting at the rising edge. 7.9.3 gpio the saa7130hl offers a set of general purpose input/output (gpio) pins, to interface to on-board peripheral circuits. these gpios are intended to take over dedicated functions: digital video port output: 8-bit or 16-bit wide (including raw dtv) transport stream input: parallel or serial (also applicable as i 2 s-bus input) peripheral interrupt input: four gpio pins of the saa7130hl can be enabled to raise an interrupt on the pci-bus. by this means, peripheral devices can directly intercept with the device driver on changed status or error conditions. any gpio pin that is not used for a dedicated function is available for direct read and write access via the pci-bus. any gpio pin can be selected individually as input or output (masked write). by these means, very tailored interfacing to peripheral devices can be created via the saa7130hl capture driver running on windows operating systems. at system reset (pci reset) all gpio pins will be set to 3-state and input, and the logic level present on the gpio pins at that moment will be saved into a special strap register. all gpio pins have an internal pull-down resistor (low level), but can be strapped externally with a 4.7 k w resistor to the supply voltage (high level). the device driver can investigate the strap register for information about the hardware configuration of a given board.
2002 dec 17 34 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 8 boundary scan test the saa7130hl has built-in logic and five dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). the saa7130hl follows the ieee std. 1149.1 - standard test access port and boundary - scan architecture set by the joint test action group (jtag) chaired by philips. the 5 special pins are: test mode select (tms), test clock (tck), test reset ( trst), test data input (tdi) and test data output (tdo). the boundary scan test (bst) functions bypass, extest, sample, clamp and idcode are all supported (see table 15). details about the jtag bst-test can be found in the specification ieee std. 1149.1 . a file containing the detailed boundary scan description language (bsdl) description of the saa7130hl is available on request. 8.1 initialization of boundary scan circuit the test access port (tap) controller of an ic should be in the reset state (test_logic_reset) when the ic is in the functional mode. this reset state also forces the instruction register into a functional instruction such as idcode or bypass. to solve the power-up reset, the standard specifies that the tap controller will be forced asynchronously to the test_logic_reset state by setting pin trst to low level. 8.2 device identi?cation codes when the idcode instruction is loaded into the bst instruction register, the identification register will be connected internally between pins tdi and tdo of the ic. the identification register will load a component specific code during the capture_data_register state of the tap controller and this code can subsequently be shifted out. at board level, this code can be used to verify component manufacturer, type and version number. the device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to tdi) and bit 0 is the least significant bit (nearest to tdo) (see fig.16). a device identification register is specified in ieee std. 1149.1b-1994 . it is a 32-bit register which contains fields for the specification of the ic manufacturer, the ic part number and the ic version number. its biggest advantage is the possibility to check for the correct ics mounted after production and determination of the version number of ics during field service. table 15 bst instructions supported by the saa7130hl instruction description bypass this mandatory instruction provides a minimum length serial path (1 bit) between pins tdi and tdo when no test operation of the component is required. extest this mandatory instruction allows testing of off-chip circuitry and board level interconnections. sample this mandatory instruction can be used to take a sample of the inputs during normal operation of the component. it can also be used to preload data values into the latched outputs of the boundary scan register. clamp this optional instruction is useful for testing when not all ics have bst. this instruction addresses the bypass register while the boundary scan register is in external test mode. idcode this optional instruction will provide information on the components manufacturer, part number and version number. handbook, full pagewidth mhc175 00000010101 0111000100110000 0001 4-bit version code 16-bit part number 11-bit manufacturer identification tdi tdo 31 msb lsb 28 27 12 11 1 0 1 mandatory fig.16 32 bits of identification code.
2002 dec 17 35 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 9 limiting values in accordance with the absolute maximum rating system (iec 60134); all ground pins connected together and grounded (0 v); all supply pins connected together. notes 1. machine model: l = 0.75 m h, c = 200 pf and r = 0 w . 2. human body model: equivalent to discharging a 100 pf capacitor through a 1.5 k w resistor. 10 thermal characteristics symbol parameter conditions min. max. unit v ddd digital supply voltage - 0.5 +4.6 v v dda analog supply voltage - 0.5 +4.6 v d v ss voltage difference between pins v ssa and v ssd - 100 mv v ia input voltage at analog inputs - 0.5 +4.6 v v i(n) input voltage at pins xtali, sda and scl - 0.5 v ddd + 0.5 v v id input voltage at digital i/o stages outputs in 3-state - 0.5 +4.6 v outputs in 3-state; 3.0v 2002 dec 17 36 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 11 characteristics v ddd = 3.0 to 3.6 v; v dda = 3.0 to 3.6 v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v ddd digital supply voltage 3.0 3.3 3.6 v v dda analog supply voltage 3.0 3.3 3.6 v p power dissipation power state d0 for typical application - 1.0 - w d0 after reset - 0.1 - w d1 - 0.2 - w d2 - 0.1 - w d3-hot - 0.02 - w crystal oscillator f xtal(nom) nominal crystal frequency crystal 1; see table 16 - 32.11 - mhz crystal 2; see table 16 - 24.576 - mhz d f xtal(n) permissible nominal frequency deviation -- 70 10 - 6 f xtal oscillator frequency range 24 32.11 33 mhz p drive crystal power level of drive at pin xtalo - 0.5 - mw t j oscillator clock jitter -- 100 ps v ih(xtali) high-level input voltage at pin xtali 2 - v ddd + 0.3 v v il(xtali) low-level input voltage at pin xtali - 0.3 - +0.8 v pci-bus inputs and outputs v ih high-level input voltage 2 - 5.75 v v il low-level input voltage - 0.5 - +0.8 v i lih high-level input leakage current v i = 2.7 v; note 1 -- 10 m a i lil low-level input leakage current v i = 0.5 v; note 1 --- 10 m a v oh high-level output voltage i o = - 2 ma 2.4 -- v v ol low-level output voltage i o = 3 or 6 ma; note 2 -- 0.55 v c i input capacitance at pin pci_clk 5 - 12 pf pin idsel -- 8pf other input pins -- 10 pf sr r output rise slew rate 0.4 to 2.4 v; note 3 1 - 5 v/ns sr f output fall slew rate 2.4 to 0.4 v; note 3 1 - 5 v/ns
2002 dec 17 37 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl t val clk to signal valid delay see fig.17; note 4 bused signals 2 - 11 ns point-to-point signals 2 - 12 ns t on ?oat-to-active delay see fig.17; note 5 2 -- ns t off active-to-?oat delay see fig.17; note 5 -- 28 ns t su input set-up time to clk see fig.17; note 4 bused signals 7 -- ns point-to-point signals 10 (12) -- ns t h input hold time from clk see fig.17 0 -- ns t rst(clk) reset active time after clk stable note 6 100 -- m s t rst(off) reset active to output ?oat delay notes 5, 6 and 7 -- 40 ns i 2 c-bus interface, compatible to 3.3 and 5 v signalling (pins sda and scl) f bit bit frequency rate 0 - 400 kbits/s v il low-level input voltage note 8 - 0.5 - 0.3v dd(i2c) v v ih high-level input voltage note 8 0.7v dd(i2c) - v dd(i2c) + 0.5 v v ol low-level output voltage i o(sink) =3ma -- 0.4 v analog video inputs i nputs ( pins cv0 to cv4) i clamp clamping current dc input voltage v i = 0.9 v - 8 -m a v i(p-p) input voltage (peak-to-peak value) note 9 0.375 0.75 1.07 v c i input capacitance -- 10 pf 9- bit analog - to - digital converters a cs channel crosstalk f i < 5 mhz --- 50 db b analog bandwidth at - 3 db; adc only; note 10 - 7 - mhz f dif differential phase ampli?er plus anti-alias ?lter bypassed - 2 - deg g dif differential gain ampli?er plus anti-alias ?lter bypassed - 2 - % le dc(d) dc differential linearity error - 1.4 - lsb le dc(i) dc integral linearity error - 2 - lsb s/n signal-to-noise ratio f i = 4 mhz; anti-alias ?lter bypassed; agc = 0 db - 50 - db enob effective number of bits f i = 4 mhz; anti-alias ?lter bypassed; agc = 0 db - 8 - bit symbol parameter conditions min. typ. max. unit
2002 dec 17 38 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl analog audio inputs (pins left1, right1, left2 and right2) and outputs (pins out_left and out_right) v i(nom)(rms) nominal input voltage (rms value) note 11 - 200 - mv v i(max)(rms) maximum input voltage (rms value) thd < 3%; note 12 - 12 v v o(max)(rms) maximum output voltage (rms value) thd<3% - 1 - v r i input resistance v i(max) = 1 v (rms) - 145 - k w v i(max) = 2 v (rms) - 48 - k w r o output resistance 150 250 375 w r l(ac) ac load resistance 10 -- k w c l output load capacitance -- 12 nf v offset(dc) static dc offset voltage - 10 30 mv thd + n total harmonic distortion-plus-noise v i =v o = 1 v (rms); f i = 1 khz; bandwidth b = 20 hz to 20 khz - 0.1 0.3 % s/n signal-to-noise ratio reference voltage v o = 1 v (rms); f i = 1 khz; itu-r bs.468 weighted; quasi peak 70 75 - db a ct crosstalk attenuation between any analog input pairs; f i = 1 khz 60 -- db a cs channel separation between left and right of each input pair 60 -- db all digital i/os: gpio pins and bst test pins (5 v tolerant) p ins gpio0 to gpio23, v_clk, gpio25 to gpio27, tdi, tdo, tms, tck and trst v ih high-level input voltage 2.0 - 5.5 v v il low-level input voltage - 0.3 - +0.8 v i li input leakage current -- 1 m a i l(i/o) i/o leakage current 3.3 v signal levels at v ddd 3 3.3 v -- 10 m a c i input capacitance i/o at high-impedance -- 8pf r pd pull-down resistance v i =v ddd - 50 - k w r pu pull-up resistance v i =0 - 50 - k w v oh high-level output voltage i o = - 2 ma 2.4 - v ddd + 0.5 v v ol low-level output voltage i o = 2 ma 0 - 0.4 v video port outputs (digital video stream from comb ?lter decoder or scaler) llc and llc2 clock output on pin v_clk (see fig.18) c l load capacitance 15 - 50 pf t cy cycle time llc active 35 - 39 ns llc2 active 70 - 78 ns symbol parameter conditions min. typ. max. unit
2002 dec 17 39 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl d duty factor c l = 40 pf; note 13 lcc active 35 - 65 % lcc2 active 35 - 65 % t r rise time 0.4 to 2.4 v -- 5ns t f fall time 2.4 to 0.4 v -- 5ns v ideo data output ( with respect to signal v_clk) on pins gpio0 to gpio17, gpio22 and gpio23 (see fig.18) c l load capacitance 15 - 50 pf t h data hold time notes 14 and 15 llc active 5 -- ns llc2 active 15 -- ns t pd propagation delay from positive edge of signal v_clk notes 14 and 15 llc active -- 28 ns llc2 active -- 55 ns raw dtv/dvb outputs (reuse of video adcs in dvb/tv applications with tda8960 and tda8961 for vsb reception) c lock input signal x_clk_in on pin gpio18 t cy cycle time 27.8 37 333 ns d duty factor note 13 40 50 60 % t r rise time 0.8 to 2.0 v -- 5ns t f fall time 2.0 to 0.8 v -- 5ns c lock output signal adc_clk on pin v_clk c l load capacitance -- 25 pf t cy cycle time 27.8 -- ns d duty factor c l =40pf 40 - 60 % t r rise time 0.4 to 2.4 v -- 5ns t f fall time 2.4 to 0.4 v -- 5ns vsb data output signals with respect to signal adc_clk c l load capacitance 25 - 50 pf t h data hold time inverted and not delayed; note 14 5 -- ns t pd propagation delay from positive edge of signal adc_clk inverted and not delayed; notes 14 and 16 -- 23 ns ts capture inputs with parallel transport streaming (ts-p); e.g. dvb applications c lock input signal ts_clk on pin gpio20 (see fig.19) t cy cycle time - 333 - ns d duty factor note 13 40 - 60 % t r rise time 0.8 to 2.0 v -- 5ns t f fall time 2.0 to 0.8 v -- 5ns symbol parameter conditions min. typ. max. unit
2002 dec 17 40 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl notes 1. input leakage currents include high-impedance output leakage for all bidirectional buffers with 3-state outputs. 2. pins without pull-up resistors must have a 3 ma output current. pins requiring pull-up resistors must have 6 ma; these are pins frame#, trdy#, irdy#, devsel#, serr#, perr#, int_a and stop#. 3. this parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. 4. req# and gnt# are point-to-point signals and have different output valid delay and input set-up times than bused signals. gnt# has a set-up time of 10 ns. req# has a set-up time of 12 ns. 5. for purposes of active or float timing measurements, the high-impedance or off state is defined to be when the total current delivered through the device is less than or equal to the leakage current specification. 6. rst is asserted and de-asserted asynchronously with respect to clk. 7. all output drivers floated asynchronously when rst is active. 8. v dd(i2c) is the extended pull-up voltage of the i 2 c-bus (3.3 or 5 v bus). 9. nominal analog video input signal is to be terminated by 75 w that results in 1 v (p-p) amplitude. this termination resistor should be split into 18 w and 56 w , and the dividing tap should feed the video input pin, via a coupling capacitor of 47 nf, to achieve a control range from - 3 db (attenuation) to +6 db (amplification) for the internal automatic gain control. see also application notes saa7130hl/34hl. 10. see the user manuals of the saa7130hl/34hl for anti-alias filter (aaf). 11. definition of levels and level setting: a) the full-scale level for analog audio signals v fs = 0.8 v (rms). the nominal level at the digital crossbar switch is defined at - 15 db (fs). b) nominal audio input levels: external, mono, v i = 280 mv (rms); - 9 db (fs). 12. the analog audio inputs (pins left1, right1, left2 and right2) are supported by two input levels: 1 v (rms) and 2 v (rms), selectable independently per stereo input pair, left1, right1 and left2, right2. 13. the definition of the duty factor: 14. the output timing must be measured with the load of a 30 pf capacitor to ground and a 500 w resistor to 1.4 v. d ata and control input signals on ts-p port ( with respect to signal ts_clk) on pins gpio0 to gpio7, gpio16, gpio19 and gpio22 (see fig.19) t su(d) input data set-up time 2 -- ns t h(d) input data hold time 5 -- ns ts capture inputs with serial transport streaming (ts-s); e.g. dvb applications c lock input signal ts_clk on pin gpio20 (see fig.19) t cy cycle time 37 -- ns d duty factor note 13 40 - 60 % t r rise time 0.8 to 2.0 v -- 5ns t f fall time 2.0 to 0.8 v -- 5ns d ata and control input signals on ts-s port ( with respect to signal ts_clk) on pins gpio16, gpio19, gpio21 and gpio22 (see fig.19) t su(d) input data set-up time 2 -- ns t h(d) input data hold time 5 -- ns symbol parameter conditions min. typ. max. unit d t h t cy -------- =
2002 dec 17 41 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 15. signal v_clk inverted; not delayed (default setup). 16. t pd = 6 ns + 0.6t adc_clk in ns (t adc_clk = 28 ns). handbook, full pagewidth mgg280 t val t on t su t h t off 1.5 v 1.5 v 1.5 v 1.5 v 2.4 v 0.4 v 0.4 v 2.4 v clk output delay 3-state output input input valid fig.17 pci i/o timing.
2002 dec 17 42 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl handbook, full pagewidth mhc002 0.4 v 2.4 v 1.5 v 0.4 v video data and control output (pins gpio0 to gpio 17, gpio 22 and gpio23 ) clock output (pin v_clk) t pd t h t h t r t f t l 2.4 v fig.18 data output timing (video data, control outputs and raw dtv/dvb). handbook, full pagewidth mhc003 0.8 v 2.0 v 1.5 v 0.8 v ts data and control input (pins gpio0 to gpio 7, gpio 16, gpio19 and gpio21) ts_clk (pin gpio20 ) 2.0 v t su(d) t h(d) t r t f fig.19 data input timing (ts data and control inputs).
2002 dec 17 43 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl table 16 speci?cation of crystals and related applications (examples); note 1 note 1. for oscillator application, see the application notes of the saa7130hl/34hl. standard crystal frequency unit 32.11 mhz 24.576 mhz fundamental 3rd harmonic fundamental 3rd harmonic 1b 1c 1a 2b 2c 2a crystal speci?cation typical load capacitance 20 8 8 20 8 10 pf maximum series resonance resistance 30 60 50 30 60 80 w typical motional capacitance 20 13.5 1.5 20 1 1.5 ff maximum parallel capacitance 73 1 4.3 7 3.3 3.5 pf maximum permissible deviation 30 10 - 6 30 10 - 6 30 10 - 6 30 10 - 6 30 10 - 6 50 10 - 6 maximum temperature deviation 30 10 - 6 30 10 - 6 30 10 - 6 30 10 - 6 30 10 - 6 20 10 - 6 external components typical load capacitance at pin xtali 33 10 15 27 5.6 18 pf typical load capacitance at pin xtalo 33 10 15 27 5.6 18 pf typical capacitance of lc ?lter n.a. n.a. 1 n.a. n.a. 1 nf typical inductance of lc ?lter n.a. n.a. 4.7 n.a. n.a. 4.7 m h
2002 dec 17 44 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 12 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.15 15.85 0.81 0.59 7 0 o o 0.12 0.2 0.1 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot425-1 136e28 ms-026 99-12-27 00-01-19 d (1) (1) (1) 20.1 19.9 h d 22.15 21.85 e z 0.81 0.59 d 0 5 10 mm scale b p e q e a 1 a l p detail x l (a ) 3 b c b p e h a 2 d h v m b d z d a z e e v m a x 102 103 y w m w m a max. 1.6 lqfp128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm sot425-1 65 64 38 39 1 128 pin 1 index
2002 dec 17 45 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 13 soldering 13.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 13.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. 13.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2002 dec 17 46 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 13.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (3) suitable plcc (4) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (4)(5) suitable ssop, tssop, vso not recommended (6) suitable
2002 dec 17 47 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl 14 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 15 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 16 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 dec 17 48 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl ics with mpeg-audio/ac-3 audio functionality ? purchase of a philips ic with an mpeg-audio and/or ac-3 audio functionality does not convey an implied license under any patent right to use this ic in any mpeg-audio or ac-3 audio application. for more information please contact the nearest philips semiconductors sales office or e-mail: licensing.cip@philips.com. ics with mpeg-2 functionality ? use of this product in any manner that complies with the mpeg-2 standard is expressly prohibited without a license under applicable patents in the mpeg-2 patent portfolio, which license is available from mpeg la, l.l.c., 250 steele street, suite 300, denver, colorado 80206. 17 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
2002 dec 17 49 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl notes
2002 dec 17 50 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl notes
2002 dec 17 51 philips semiconductors product speci?cation pci video broadcast decoder saa7130hl notes
? koninklijke philips electronics n.v. 2002 sca74 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 753505/02/pp 52 date of release: 2002 dec 17 document order number: 9397 750 10358

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